1. Field of the Invention
The present invention relates to semiconductor packaging technology, and more particularly, to a leadframe with a dot array of silver-plated regions on die pad, which is designed specifically for use in the construction of an exposed-pad type of semiconductor package.
2. Description of Related Art
A leadframe is a metal-made frame that includes a centrally-located die pad and a plurality of peripherally-located leads surrounding the die pad. The die pad is used for mounting a semiconductor die (chip) while the leads are used to serve as external connecting means for the semiconductor chip. After the semiconductor chip is wire-bonded to the leads, the die pad together with the semiconductor chip are encapsulated in an epoxy-molded compound (EMC) to form a semiconductor package.
An exposed-pad type of semiconductor package is characterized by that the die pad of the leadframe has its back side exposed to the bottom outside of the encapsulation body. During SMT (Surface Mount Technology) process when the exposed-pad semiconductor package is mounted on a printed circuit board (PCB), it allows the exposed back side of the die pad to be directly soldered to the PCB""s ground plane, thereby allowing the semiconductor chip enclosed in the encapsulation body to have a better grounding effect.
FIG. 1 is a schematic sectional diagram showing a conventional exposed-pad type of semiconductor package. As shown, this semiconductor package comprises: (a) a leadframe 1, which is typically made of copper, and which includes a die pad 10, an inner-lead portion 20, and an outer-lead portion 30; the die pad 10 having a front side 10a and a back side 10b, and whose front side 10a is partitioned into a centrally-located die-mounting area 11 and a peripherally-located ground-wire bonding area 12; (b) a silver-epoxy layer 50 pasted over the die-mounting area 11 of the die pad 10; (c) a semiconductor chip 60 having an active surface 60a and an inactive surface 60b, and whose inactive surface 60b is adhered by means of the silver-epoxy layer 50 to the die-mounting area 11 of the die pad 10; (c) a plurality of bonding wires 70, including a set of I/O wires 71 bonded from the active surface 60a of the semiconductor chip 60 to the inner-lead portion 20 of the leadframe 1 and at least one ground wire 72 down bonded from the active surface 60a of the semiconductor chip 60 to the ground-wire bonding area 12 of the die pad 10; and (d) an encapsulation body 80 which encapsulates the semiconductor chip 60 together with the inner-lead portion 20, the silver-epoxy layer 50, the bonding wires 70, and the front side 10a of the die pad 10, while exposing the back side 10b of the die pad 10 to the outside. This semiconductor package is customarily referred to as exposed-pad type due to the fact that the back side 10b of the die pad 10 is exposed to the outside of the encapsulation body 80.
During SMT process when the exposed-pad semiconductor package is mounted on a PCB 90 having a ground plane 91, the exposed back side 10b of the die pad 10 can be directly soldered to the ground plane 91 so as to establish a direct grounding path for the packaged semiconductor chip 60.
Conventionally, the leadframe 1 can be plated with silver so as to increase its wire bondability. Presently, there are two plating schemes to serve this purpose: a ring plating scheme and a spotted plating scheme, which are respectively depicted in the following with reference to FIG. 2A and FIG. 2B.
As shown in FIG. 2A, by the ring plating scheme, silver is selectively plated over the ground-wire bonding area 12 of the die pad 10 and over the inner-lead portion 20 of the leadframe 1, while leaving the die-mounting area 11 unplated (the silver-plated areas are illustrated as shaded areas in FIG. 2A). This ring plating scheme is advantageous in that it allows the silver-epoxy layer 50 to be more securely adhered to the die-mounting area 11 of the die pad 10 without delamination (this is because that epoxy adheres to copper better than to silver); but has the drawback of a reduced electrically coupling effect between the inactive surface 60b of the semiconductor chip 60 and the die pad 10, undesirably resulting in a reduced grounding effect for the semiconductor chip 60.
As shown in FIG. 2B, by the spotted plating scheme, silver is selectively plated over the while of the die-mounting area 11, the whole of the ground-wire bonding area 12, and the inner-lead portion 20 (the silver-plated areas are illustrated as shaded areas in FIG. 2B). This spotted plating scheme is advantageous in that it allows a better electrically coupling effect between the active surface 60a of the semiconductor chip 60 and the die pad 10, but has the drawback of making the silver-epoxy layer 150 easily subjected to delamination from the die pad 10.
Related patents, include, for example, the U.S. Pat. No. 5,153,706 entitled xe2x80x9cLEAD FRAMES FOR USE IN PLASTIC MOLD TYPE SEMICONDUCTOR DEVICESxe2x80x9d. This patent discloses a leadframe whose die pad is metal-plated on the edge areas opposite to the inner leads, while leaving the centrally-located die-mounting area unplated. Undesirably, however, since this plating scheme is substantially the same as the ring plating scheme depicted in FIG. 2A, the utilization of this patent nevertheless has the same drawback.
It is therefore an objective of this invention to provide a leadframe with a dot array of silver-plated regions on die pad, which allows the semiconductor chip to be more securely adhered to the die pad without delamination and also allows the inactive surface of the semiconductor chip to be better electrically coupled to the die pad to provide a better grounding effect.
In accordance with the foregoing and other objectives, the invention proposes a leadframe with a dot array of silver-plated regions on die pad for use in the construction of an exposed-pad semiconductor package.
Broadly recited, the leadframe of the invention comprises: (a) a die pad having a front side and a back side, and whose front side is partitioned into a centrally-located die-mounting area and a peripheral area surrounding the die-mounting area; wherein the die-mounting area of the die pad is selectively metal-plated to form a dot array of metal-plated regions; and the peripheral area of the die pad is entirely metal-plated to form a metal-plated peripheral area; and (b) a plurality of leads surrounding the die pad; the leads including an inner-lead portion and an outer-lead portion; wherein the inner-lead portion of each of the leads is metal-plated to form a metal-plated lead area.
In addition, the die-mounting area of the die pad can be further formed with a plurality of dimples for the purpose of increasing the contact area between the die pad and a silver-epoxy layer that is to be pasted over the die-mounting area for use to adhere a semiconductor chip to the die pad.
By using the leadframe of the invention in the construction of an exposed-pad semiconductor package, owing to the provision of the dot array of silver-plated regions within the die-mounting area of the die pad, it allows a better electrical coupling between the die pad and the inactive surface of the semiconductor chip than the prior art of FIG. 2A so that the packaged semiconductor chip can have a better grounding effect, and also allows the silver-epoxy layer to be better adhered to the die pad than the prior art of FIG. 2B to prevent delamination. Moreover, owing to the additional provision of the dimples within the die-mounting area of the die pad, it allows an increased contact area between the die-mounting area and the silver-epoxy layer, so that the silver-epoxy layer can be more strongly adhered to the die-mounting area without delamination.